Susmita Sur-Kolay

Susmita Sur-Kolay received a B.Tech.(Hons.) degree in Electronics and Electrical Communications Engineering from Indian Institute of Technology Kharagpur and a Ph.D. degree in Computer Science and Engineering from Jadavpur University India. She has been a faculty member in the Advanced Computing and Microelectronics Unit of the Indian Statistical Institute, Kolkata, India since 1999 and has recently superannuated as a Professor (HAG). During the period 1993-99, she was a Reader in the Department of Computer Science and Engineering of Jadavpur University. Prior to that, she was a post-doctoral fellow at University of Nebraska-Lincoln, and a Research Assistant at the Laboratory for Computer Science in Massachusetts Institute of Technology. She was also on sabbatical at University of Bremen, Princeton University and Intel Corp., USA.

Susmita Sur-Kolay has a broad research portfolio with theory meets practice as the keystone. Her research contributions are in the areas of algorithmic design automation for electronic and quantum circuits, fault modeling and testing, hardware security and graph algorithms. She has shown multi-faceted excellence in engineering innovation and remarkable leadership in dissemination of knowledge in her fields of expertise. As one of the global leaders in the area of physical design of ICs which form the core of most modern technological advances, her fundamental insights into inherent nonslicibility of floorplans for ASICs and FPGAs have led to several publications, and have inspired leading EDA companies to consider adopting her methods in their software tools. Her work on fault modeling and test pattern generation for timing faults due to power supply droop considering both logic and physical design have led to successful sponsored research collaborations. She has established herself as a leading edge thinker on hardware security for IC chips and SoCs and IoT-based health care informatics, which are of significant interest to leading companies for secure biomedical services. Susmita has extended her expertise to pioneer algorithmic synthesis, including placement of quantum circuits. Her works span methodologies for both technology independent and dependent stages of the design flow considering the unique constraints of quantum technology. Quantum resource minimization and error correction have been addressed in her work on physical design for this new paradigm of computing. She has co-authored several technical papers in leading international journals and refereed conference proceedings, a chapter in the Handbook on Algorithms for VLSI Physical Design Automation, three book chapters and co-edited three books.

In addition to being an excellent researcher, Susmita is an outstanding teacher, and has delivered numerous invited talks and tutorials worldwide. She was the Technical Program Co-Chair of the 18th International Conference on VLSI Design (2005), the 11th Symposium on VLSI Design and Test (2007), ISVLSI 2011 and General Co-Chair of the 29th International Conference on VLSI Design (2016). She has served on the program committees of several international conferences, and on the editorial board of the IET Computers and Digital Techniques, IEEE Transactions on VLSI Systems and ACM Transactions on Embedded Computing Systems. She was a Distinguished Visitor of IEEE Computer Society (India), and is a Senior Member of IEEE, Fellow of Indian National Science Academy (INSA) and Indian National Academy of Engineering (INAE), Member of ACM, IET and VLSI Society of India. Among other awards, she was the recipient of the President of India Gold Medal (summa cum laude) at IIT Kharagpur (1980), IBM Faculty Award (2009), Distinguished Alumnus Award (2020), Women in Technology Leadership Award from VLSI Society of India (2022) and International Excellence Fellowship at Karlsruhe Institute of Technology (2024).